In a digital signal transmission system that uses direct spread spectrum sequence, bits “0” and “1” are encoded using respective signals of a length that depends on the spread sequence used and then sent by the transmitter. The symbols are then received and decoded, at the receiver level, by the DSSS decoder that traditionally comprises a finite response filter.
In the case where the bits are encoded using an N-length Barker code, the symbols that encode bits “0” and “1” each appear in the form of a sequence of N symbol elements (“0” or “1”) called “chips”, distributed over one or another of two different levels (−1 and 1) and delivered at a predetermined fixed frequency F.
The symbol elements that encode bit “1” are negatively correlated to the corresponding symbol elements that encode bit “0”; that is, the same-level symbol elements in one or another of these symbols have opposite values.
For example, insofar as a symbol element of the symbol that encodes bit “1” is at level 1, the symbol element corresponding to the symbol that encodes bit “0” is at level −1. Likewise, insofar as a symbol element of the symbol that encodes bit “1” is at level −1, the symbol element corresponding to the symbol that encodes bit “0” is at level 1.
The spread binary message is then used to phase-modulate the carrier, presenting itself in the form of a time function sinusoidal wave expressed as p(t), p(t)=cos(2nfp.t+φ), where fp is its frequency and φ is its phase at the source.
FIG. 1 illustrates the architecture of a reception string in a transmission system that uses direct spread spectrum sequence. This architecture traditionally leads to interfacing analogue radio modules 2 with a digital processing system that includes a DSSS decoder 3. Thus, the digital system is first captured by an antenna 1, then transmitted to the radio-frequency analog block 2 of the string.
The radio-frequency analog block typically includes a low-noise amplifier, a local oscillator attached to a mixer, cooperating to return the baseband signal, and a filtering stage. More specifically, at the output of the mixer, the binary message is available in continuous form in baseband, added to a high frequency component based on twice the carrier frequency. Indeed, this demodulation operation causes the appearance of the spectral pattern of the baseband signal, but also at twice the demodulation frequency; that is, around the frequency 2fp. Furthermore, a low-pass filtering stage is necessary at the output of the mixer in order to eliminate the harmonic distortion owing to the spectrum redundancy during the signal's demodulation. Therefore, at the output of the passband filter, only the baseband message is found; that is, returned around the frequency 0.
The resulting signal is then digitalized by an analog/digital converter (CAN). It is sampled at a sampling frequency that respects the Shannon limit. In other words, the sampling frequency is taken as being equal to at least twice the maximum frequency presented by the power spectrum density of the message spread over the baseband.
The operation of the elements described briefly above is not modified within the framework of this invention, and these elements will not be described in further detail.
At the CAN output, the signal is then sent to the DSSS decoder 3, allowing the recovery of the synchronization of the signal to be decoded with respect to the payload. More specifically, it is a finite impulse response filter, characterized by the coefficients (ai)i=0,1,—,n of its impulse response. The decoding procedure based on the finite impulse response filter includes matching the result of coefficients ai with the exact mirrored filter of the chosen spread code.
This type of filter, illustrated in FIG. 2, typically includes a sampler for capturing a sample of the input digital signal IN. The filter is ideally clocked at the same sampling frequency than that of the incoming signal. Its structure is that of an offset register REG that receives each sample of the input signal IN. The offset register includes N switches in the case of symbols with N symbol elements, which cooperate with a combinational circuit COMB, designed in a manner known by those skilled in the art, and utilizing the results of coefficients ai so that the output signal OUT produced by the same filter presents an amplitude that directly depends on the level of correlation found between the sequence of the last N samples captured by this filter and the sequence of N symbol elements of one of the two symbols, for example, the sequence of N elements of the symbol that encodes bit “1” of the digital signal.
Thus, the results of coefficients ai including the exact replica of the chosen spread code allow the correlation of the level of the symbol elements received in succession by the filter at its input, at the levels of the successive symbols of one of the two symbols used to encode bits “0” and “1”, for example, symbol elements of the symbol that encodes bit “1”.
Thus, for a Barker code with a length of N=11, each symbol is composed of 11 symbol elements such as A to K and A′ to K′, represented by the solid lines in FIG. 1, respectively for a bit “1” and for a bit “0”.
If, for example, the filter receives in succession the symbol elements A″ to K″, composed in the same manner by symbol elements A′ to K′ forming the symbol that encodes bit 0, the output signal that it will deliver by correlating these symbol elements with the symbol elements A to K will have an amplitude equal to −11; this total being represented by the sum of the 11 negative correlation basic values equal to −1, where the first one provides the negative correlation between A″ (level 1) and A (level −1), where the second provides the negative correlation between B″ (level 1) and B (level −1), and so on, and where the eleventh provides the negative correlation between K″ (level 1) and K (level −1).
Therefore, it can be noted that the symbol that encodes bit 0 at the input of the filter manifests itself on output by a spike with a value of −11, and in the same manner, the symbol that encodes bit 1 at the input of the filter manifests itself on output by a spike with a value of 11.
The output of the finite impulse response filter therefore provides synchronization spikes, where the sign gives the value of the source message bit at this time: if the spike is negative, it is “0”, if the spike is positive, it is “1”.
In order to transform the symbols decoded in this manner into a binary data stream that corresponds to the source message, and in order to associate to this data stream a related synchronization clock for capturing data, these spikes are passed through hysteresis comparators, 4 and 5, respectively. The data of the source message encoded over a bit, as well as the data capture clock signal, is therefore restored at the output of hysteresis comparators 4 and 5.
FIG. 5 can now be referenced, which shows the output signal of the data comparator 4, labeled comp_data, the output signal of the clock comparator 5, labeled CLK, and the output signal of the DSSS decoder, labeled output_DSSS, applied at the input of the comparators. The lower and upper threshold values of the comparators, respectively labeled low and up, are represented as horizontal dotted lines at the level of the DSSS output signal.
In the above example, the output signal of the DSSS decoder 3 is delivered to the data comparator 4, suitable for comparing the amplitude of this output signal with a lower threshold value low, for example, fixed at −8, and an upper threshold value up, for example, fixed at +8. The data comparator 4 therefore delivers, as an output digital signal comp_data representative of a decoded symbol of the input signal applied to the decoder, a first bit “1” when the amplitude of the output signal of the DSSS decoder is greater than the upper threshold value up, and a second bit “0” when the amplitude of the output signal of the DSSS decoder is lower than the lower threshold value low.
The output signal of the DSSS decoder 3 is also applied to a second comparator 5. This clock comparator 5 switches as soon as the amplitude of the output signal of the DSSS decoder passes above or below the lower threshold value low and as soon as the signal passes above or below the upper threshold value up and therefore provides a digital signal CLK to a bit that serves as a capture clock for the data. It should be noted that the lower and upper threshold values can be adjusted.
The output signals of comparators 4 and 5 are then processed by the receiver 6, which is rated to capture a data element of the data signal generated at the output of the data comparator 5, for example, at each pulse edge of the clock signal generated by the clock comparator 4. The comparator is designed to implement a certain number of operations, such as: detection of the message “start” or “stop”, descrambling, message error correction, data storage, etc. The “start” and “stop” sequences of the message can be a specific sequence of bits, but it may also not contain the stop sequence if the length of the message is known ahead of time. Error correction can be performed using known techniques, such as the use of a cyclic redundancy check (CRC), the use of parity, and the use of Reed-Solomon type error corrector codes.
The CPU 7 (microprocessor) reads the data received by the receiver, as well as any additional information if it exists (communication status, interruption, detected errors, etc.)
Nevertheless, this reception device can only operate correctly if the output signal of the DSSS decoder, which is supplied at the input of the comparators, does not contain too many errors.
For example, still within the framework of the example in FIG. 3, if the DSSS decoder successively receives symbol elements A″ to J″ composed identically by symbol elements A′ to J′, and a last symbol element K″ equal to zero following a transmission problem, the output signal that it will deliver by correlating these symbol elements with the symbol elements A to K will only have an amplitude equal to −9, the symbol element K″ making a contribution of +1 to this output signal.
Of course, the situation would be exactly the same if the missing symbol element was not K″ but rather any of the other symbol elements.
Similarly if, for example, the filter successively received symbol elements A″ to I″ composed identically of symbol elements A to I, and the last two symbol elements J″ and K″ are equal to zero following a transmission problem, the output signal that it delivers by correlating these symbol elements with the symbol elements A to K will have an amplitude equal to +7, this total being represented by the sum of the 9 basic correlation values equal to +1, where the first provides the correlation between A″ (level −1) and A (level −1), where the second provides the correlation between B″ (level −1) and B (level −1), etc., and where the ninth provides the correlation between I″ (level 1) and I (level 1), the symbol elements J″ and K″ making a contribution of −2 to this output signal.
Under these conditions, with a lower threshold value fixed at −8 and an upper threshold value fixed at +8, the receiver will incorporate a symbol that encodes bit “1”, the reception of successive symbol elements A″ and K″ having only 10 symbol elements that are correlated to symbol elements A to K (instead of 11), and will incorporate a symbol that encodes bit “0”, the reception of successive symbol elements A″ and K″ having only 10 symbol elements that are negatively correlated to symbol elements A to K (instead of 11).
Therefore, it can be observed that the transmission faults that produce errors in the signal received can, to a certain extent, be overcome by adjusting the lower and upper thresholds of the comparators to intermediate values, for example greater than or equal to 8 and lower than or equal to −8 in the case of an N length Barker encoding equal to 11. To do this, the input signal is ideally not significantly altered by the transmission faults.
Indeed, when the received input signal of the DSSS decoder has too many errors, the spikes at the output of the decoder are therefore much lower and could be below the comparator thresholds. Therefore, there is a risk of introducing errors because certain clock pulse edges will be missing and the data will be false.
This phenomenon is illustrated in FIG. 5, which shows the output of the DSSS decoder when errors are present. The output signal of the DSSS decoder therefore passes by a negative spike in which the value is greater than the lower threshold of the comparators. Therefore, this results in a clock loss at the output signal CLK level of the clock comparator and, also, a false data element at the moment in which the clock pulse edge should have been produced.
It is possible to lower the comparator thresholds, but this would risk, with threshold values that are too low, taking into account output spikes of the DSSS decoder that represent errors and thus generating unwanted clock pulse edges at the output of the clock comparator and additional data.
Also, a correction system can be implemented using very powerful correction codes, but this would have the inconvenience of using large amounts of processing power.
Another possibility would be to use wider spread codes to free these errors, but this would negatively affect the bit rate.
Furthermore, the loss of a clock pulse edge at the output of the clock comparator creates an offset in the subsequent bits that compose the received signal, which makes error correction very difficult. For example, if an 8-bit message is sent: “10101010” and a clock pulse edge is lost, “1011010” could be received. Therefore, 90 is received instead of 170.